This invention relates generally to semiconductor devices performing analog-to-digital conversion functions, and, more specifically, to an improved sample and hold circuit for analog-to-digital converters that is both high speed and low power.
Sample and hold circuits are typically implemented in the acquisition stage of the analog-to-digital conversion process. One such implementation is known in the art as the successive approximation register (SAR) approach. In this approach a sample of the incoming analog signal amplitude is captured and made available to an input node (analog) of a comparator. The second input node of the comparator (high gain amplifier) is connected to a capacitor divider array which in turn is connected to a register. The voltage at the second node is varied by manipulating the stored value of the register until voltage equivalence is achieved. Once the voltage equivalence is achieved the comparator output will change states and the digital equivalent can be captured and stored by the subsequent circuitry.
In a similar architecture, the sampling capacitor is comprised of an array of capacitors and serves a dual purpose. First, during the sampling phase, one side (input) of all the capacitors in the array are connected by switches to the input voltage Vin. Then during the conversion phase, various combinations of the input sides of the capacitor array are connected either low (GND) or high (full scale voltage). At all times the other side (output) of the capacitors are connected to the first node of the comparator. The second node of the comparator is connected to a reference voltage. Again the results of the comparisons control the successive approximation register and thus the switched capacitor array.
Referring to FIG. 1, a sample and hold circuit is designed to capture the voltage amplitude of a slice of the incoming analog signal with the highest fidelity, lowest power and quickest speed possible before the successive approximation occurs. In the prior art, the incoming analog signal, VIN, was sampled by means of a switch 10 to create a periodic pulse and then converted to a held signal by a capacitor 20. In this example, capacitor 20 is both the sample capacitor and the switched array as described hereinabove. The hold signal was then sent to an input node of an operational amplifier 30. The second node of the operational amplifier was connected to a reference voltage, which may be the full scale voltage or ground in a bipolar system, or for a single supply device VDD/2. A feedback loop 40 was created between the output of the operational amplifier 30 and the analog sample input for zeroing the offset of the amplifier as the input voltage varied. A switch 50 was used to connect the feedback loop 40 at a corresponding time that the sample switch 10 connected the input of the operational amplifier 30 and the input signal, Vin. The output of the operational amplifier was also connected to the successive approximation comparator described hereinabove.
In this regard the prior art was inadequate because rapid acquisition is limited by the slew rate of the operational amplifier. The slew rate of the operational amplifier, i.e., the time it takes the operational amplifier to slew or vary the output from one voltage extreme to another (DV/Dt), is determined in part by the current required to charge the sampling capacitor after switch 10 closes. The undesirable trade off was high power to supply the current necessary to drive the output voltage expeditiously or low power which resulted in undesirably long slew rates. Alternatively, an amplifier can be used with a class AB output stage. The class AB output could relax the slew rate problem. However, it would create a new problem. During the conversion process there often arises circumstances where the amplifier must correctly compare a very small input difference after previously comparing a large input difference of the opposite sign. A low power amplifier with a class AB output stage has a long recovery time in that situation. Thus it is likely that the recovery time would then become the speed limiting factor, rather than the sampling time for this type of analog to digital converter. Therefor, a need exists to provide an improved sample and hold circuit that is capable of rapid acquisition and low power operation.
The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing an improved sample and hold circuit for analog to digital conversion applications, capable of rapid data sample acquisition, and operates at low power.
In accordance with one embodiment of the present invention (see FIG. 2), an improved sample and hold circuit is comprised of an input VIN and a ground potential input GND, an input sampling switch 110 coupled to the input VIN, a ground switch 112 coupled to the ground input GND, an input sampling capacitor 120 of the switched array style coupled to the input sampling switch 110, a ground sampling capacitor 122 coupled to the ground switch 122; a first operational amplifier 160 having a first input 168 connected to the input sampling capacitor 120 and to a pre-charge switch 150, and a second input 170 connected to the ground sampling capacitor 122 and to a second pre-charge switch 152; a low power second operational amplifier 130 having a first input 172 connected to the output of the first operational amplifier 160 and a second input 174 connected to the second input 162 of the first operational amplifier 160 (which also is connected to the ground potential capacitor 122), and first and second feedback loops 140, 144 for the second operational amplifier 130 where both the first and second feedback loops 140, 144 are switchable with switches 142 and 146, respectively.
In accordance with another embodiment of the present invention the inputs 168, 170 of the first operational amplifier 160 are pre-charged to a reference voltage, Vcm, prior to the acquisition of the analog input signal, VIN.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.